-- ***************************************************************************** -- BSDL file for design isl3893 -- Created by Synopsys Version 2002.05-SP1 (Aug 12, 2002) -- Designer: -- Company: -- Date: Mon Nov 18 13:52:36 2002 -- ***************************************************************************** entity isl3893 is -- This section identifies the default device package selected. generic (PHYSICAL_PIN_MAP: string:= "BGA316"); -- This section declares all the ports in the design. port ( ETH1_COL : in bit; ETH1_CRS : in bit; ETH1_RXCLK : in bit; ETH1_RXDV : in bit; ETH1_RXER : in bit; ETH1_TXCLK : in bit; HFCLK : in bit; MIRDY : in bit; PCI_GNT_N : in bit; PCI_IDSEL : in bit; PCI_RST_N : in bit; TCK : in bit; TDI : in bit; TMS : in bit; TRST_N : in bit; ETH1_RXD : in bit_vector (0 to 3); ETH_MDIO : inout bit; PCI_CLK : inout bit; PCI_DEVSEL_N : inout bit; PCI_FRAME_N : inout bit; PCI_IRDY_N : inout bit; PCI_PAR : inout bit; PCI_PERR_N : inout bit; PCI_STOP_N : inout bit; PCI_TRDY_N : inout bit; GP1 : inout bit_vector (0 to 15); GP2 : inout bit_vector (0 to 15); GP3 : inout bit_vector (0 to 7); MID : inout bit_vector (0 to 15); PCI_AD : inout bit_vector (0 to 31); PCI_CBE_N : inout bit_vector (0 to 3); PCI_INTA_N : out bit; PCI_PME_N : out bit; PCI_REQ_N : out bit; PCI_SERR_N : out bit; TDO : out bit; ETH1_TXEN : buffer bit; ETH_MDC : buffer bit; LNA_HIGHGAIN : buffer bit; MIAA : buffer bit; MICLKEN : buffer bit; MIOE : buffer bit; MISA : buffer bit; MIWE : buffer bit; ETH1_TXD : buffer bit_vector (0 to 3); MIA : buffer bit_vector (0 to 15); MIBLS : buffer bit_vector (0 to 3); MICS : buffer bit_vector (0 to 3); COMPioff : linkage bit; COMPiq : linkage bit; COMPpabias : linkage bit; COMPrx : linkage bit; COMPtx : linkage bit; FSADiq : linkage bit; FSADoff : linkage bit; FSADpabias : linkage bit; FSADrx : linkage bit; FSADtx : linkage bit; GNDA1 : linkage bit; GNDA3 : linkage bit; GNDA4 : linkage bit; GNDA5 : linkage bit; GNDA6 : linkage bit; GNDAPLL : linkage bit; GNDD0 : linkage bit; GNDD1 : linkage bit; Iin_N : linkage bit; Iin_P : linkage bit; Ioout_N : linkage bit; Ioout_P : linkage bit; Iout_N : linkage bit; Iout_P : linkage bit; Iref : linkage bit; LOOP132 : linkage bit; LOOP44 : linkage bit; LOOP80 : linkage bit; MICLK : linkage bit; PA_det : linkage bit; PAbias2G : linkage bit; PAbias5G : linkage bit; Qin_N : linkage bit; Qin_P : linkage bit; Qoout_N : linkage bit; Qoout_P : linkage bit; Qout_N : linkage bit; Qout_P : linkage bit; RESET_N : in bit; RX_IF_det : linkage bit; RX_IFagc_N : linkage bit; RX_IFagc_P : linkage bit; TMSEL : in bit_vector (4 to 5); TSTCLK132 : linkage bit; TSTCLK44 : linkage bit; TSTCLK80 : linkage bit; TX_IFagc : linkage bit; TX_IQ_det : linkage bit; VD33 : linkage bit; VDDA1 : linkage bit; VDDA2 : linkage bit; VDDA3 : linkage bit; VDDA4 : linkage bit; VDDA5 : linkage bit; VDDA6 : linkage bit; VDDAPLL : linkage bit; VDDD0 : linkage bit; VDDD1 : linkage bit; VREF : linkage bit; VSUB1 : linkage bit; VSUB2 : linkage bit; gnd : linkage bit; vdd : linkage bit ); use STD_1149_1_1994.all; attribute COMPONENT_CONFORMANCE of isl3893: entity is "STD_1149_1_1993"; attribute PIN_MAP of isl3893: entity is PHYSICAL_PIN_MAP; -- This section specifies the pin map for each port. This information is -- extracted from the port-to-pin map file that was read in using the -- "read_pin_map" command. constant BGA316: PIN_MAP_STRING := "ETH1_COL : V3," & "ETH1_CRS : T3," & "ETH1_RXCLK : U3," & "ETH1_RXDV : W1," & "ETH1_RXER : Y3," & "ETH1_TXCLK : U2," & "HFCLK : K17," & "MIRDY : E16," & "PCI_GNT_N : H5," & "PCI_IDSEL : B10," & "PCI_RST_N : H1," & "TCK : K20," & "TDI : L20," & "TMS : L19," & "TRST_N : L17," & "ETH1_RXD : (V4, W3, W2, Y1)," & "ETH_MDIO : U1," & "PCI_CLK : H2," & "PCI_DEVSEL_N : J4," & "PCI_FRAME_N : A9," & "PCI_IRDY_N : E9," & "PCI_PAR : D9," & "PCI_PERR_N : J1," & "PCI_STOP_N : K5," & "PCI_TRDY_N : D10," & "GP1 : (M19, M20, M18, M16, N19, N17, N16, P19, P20, P18, " & "P17, R19, R20, R18, R16, T19)," & "GP2 : (P3, P4, P5, M2, P1, N2, N1, M3, M4, M1, L2, L4, L5" & ", L1, K1, K3)," & "GP3 : (T20, T18, U17, U19, U20, U16, V20, W20)," & "MID : (B19, A20, B20, E18, D20, E19, E20, F19, F17, F16, " & "G18, G17, G16, J19, H17, H16)," & "PCI_AD : (G3, G5, F2, F1, F4, F5, E2, E1, E3, E5, D1, D5, C1" & ", C3, D3, B1, C2, A1, C4, A2, B4, A3, A4, A5, B6, C6, D6, A6, B7, " & "C7, E7, B9)," & "PCI_CBE_N : (C8, D8, B8, E8)," & "PCI_INTA_N : J5," & "PCI_PME_N : G1," & "PCI_REQ_N : H3," & "PCI_SERR_N : C10," & "TDO : L16," & "ETH1_TXEN : R5," & "ETH_MDC : T2," & "LNA_HIGHGAIN : K16," & "MIAA : B18," & "MICLKEN : D17," & "MIOE : B17," & "MISA : A17," & "MIWE : A19," & "ETH1_TXD : (T1, R2, R3, R4)," & "MIA : (B12, A12, E12, B13, A13, D13, E13, B14, D14, E14, " & "B15, A15, C15, D15, C16, D16)," & "MIBLS : (H20, J18, J17, J20)," & "MICS : (B11, C11, D11, E11)," & "COMPioff : T6," & "COMPiq : U8," & "COMPpabias : Y18," & "COMPrx : T13," & "COMPtx : V13," & "FSADiq : T10," & "FSADoff : U5," & "FSADpabias : Y17," & "FSADrx : W13," & "FSADtx : U13," & "GNDA1 : V5," & "GNDA3 : T8," & "GNDA4 : Y12," & "GNDA5 : W12," & "GNDA6 : W17," & "GNDAPLL : Y16," & "GNDD0 : W4," & "GNDD1 : U14," & "Iin_N : W7," & "Iin_P : Y7," & "Ioout_N : W6," & "Ioout_P : V6," & "Iout_N : Y10," & "Iout_P : W10," & "Iref : T7," & "LOOP132 : T15," & "LOOP44 : W15," & "LOOP80 : W16," & "MICLK : C18," & "PA_det : U11," & "PAbias2G : W19," & "PAbias5G : Y20," & "Qin_N : Y8," & "Qin_P : W8," & "Qoout_N : Y5," & "Qoout_P : W5," & "Qout_N : Y11," & "Qout_P : W11," & "RESET_N : K4," & "RX_IF_det : T11," & "RX_IFagc_N : Y13," & "RX_IFagc_P : V12," & "TMSEL : (V19, Y19)," & "TSTCLK132 : N5," & "TSTCLK44 : C20," & "TSTCLK80 : H18," & "TX_IFagc : Y14," & "TX_IQ_det : V11," & "VD33 : E4," & "VDDA1 : T5," & "VDDA2 : U6," & "VDDA3 : U7," & "VDDA4 : V8," & "VDDA5 : V10," & "VDDA6 : W18," & "VDDAPLL : V15," & "VDDD0 : Y4," & "VDDD1 : V14," & "VREF : Y9," & "VSUB1 : U4," & "VSUB2 : T14," & "gnd : D4," & "vdd : D2"; -- This section specifies the TAP ports. For the TAP TCK port, the parameters in -- the brackets are: -- First Field : Maximum TCK frequency. -- Second Field: Allowable states TCK may be stopped in. attribute TAP_SCAN_CLOCK of TCK : signal is (1.000000e+07, BOTH); attribute TAP_SCAN_IN of TDI : signal is true; attribute TAP_SCAN_MODE of TMS : signal is true; attribute TAP_SCAN_OUT of TDO : signal is true; attribute TAP_SCAN_RESET of TRST_N: signal is true; -- Specifies the compliance enable patterns for the design. It lists a set of -- design ports and the values that they should be set to, in order to enable -- compliance to IEEE Std 1149.1 attribute COMPLIANCE_PATTERNS of isl3893: entity is "(RESET_N, TMSEL(4), TMSEL(5)) (100)"; -- Specifies the number of bits in the instruction register. attribute INSTRUCTION_LENGTH of isl3893: entity is 4; -- Specifies the boundary-scan instructions implemented in the design and their -- opcodes. attribute INSTRUCTION_OPCODE of isl3893: entity is "BYPASS (1111, 1110)," & "EXTEST (0000)," & "SAMPLE (0010)," & "USER1 (0011)," & "USER2 (0100)," & "USER3 (0110)," & "USER4 (1000)," & "USER5 (1010)," & "USER6 (1011)," & "RUNBIST (1100)," & "USER7 (1101)," & "USER8 (0101)," & "USER9 (0111)," & "USER10 (1001)," & "IDCODE (0001)"; -- Specifies the bit pattern that is loaded into the instruction register when -- the TAP controller passes through the Capture-IR state. The standard mandates -- that the two LSBs must be "01". The remaining bits are design specific. attribute INSTRUCTION_CAPTURE of isl3893: entity is "0001"; -- Specifies the bit pattern that is loaded into the DEVICE_ID register during -- the IDCODE instruction when the TAP controller passes through the Capture-DR -- state. attribute IDCODE_REGISTER of isl3893: entity is "0000" & -- 4-bit version number "0000111100110101" & -- 16-bit part number "00000001011" & -- 11-bit identity of the manufacturer "1"; -- Required by IEEE Std 1149.1 -- This section specifies the test data register placed between TDI and TDO for -- each implemented instruction. attribute REGISTER_ACCESS of isl3893: entity is "BYPASS (BYPASS, USER8, USER9, USER10)," & "BOUNDARY (EXTEST, SAMPLE, USER1, USER2, USER3, USER4, USER5, USER6, " & "RUNBIST, USER7)," & "DEVICE_ID (IDCODE)"; -- Specifies the length of the boundary scan register. attribute BOUNDARY_LENGTH of isl3893: entity is 362; -- The following list specifies the characteristics of each cell in the boundary -- scan register from TDI to TDO. The following is a description of the label -- fields: -- num : Is the cell number. -- cell : Is the cell type as defined by the standard. -- port : Is the design port name. Control cells do not have a port -- name. -- function: Is the function of the cell as defined by the standard. Is one -- of input, output2, output3, bidir, control or controlr. -- safe : Specifies the value that the BSR cell should be loaded with -- for safe operation when the software might otherwise choose a -- random value. -- ccell : The control cell number. Specifies the control cell that -- drives the output enable for this port. -- disval : Specifies the value that is loaded into the control cell to -- disable the output enable for the corresponding port. -- rslt : Resulting state. Shows the state of the driver when it is -- disabled. attribute BOUNDARY_REGISTER of isl3893: entity is -- -- num cell port function safe [ccell disval rslt] -- "361 (BC_1, ETH1_RXER, input, X), " & "360 (BC_1, ETH1_COL, input, X), " & "359 (BC_1, ETH1_RXD(0), input, X), " & "358 (BC_1, ETH1_RXD(1), input, X), " & "357 (BC_1, ETH1_RXD(2), input, X), " & "356 (BC_1, ETH1_RXD(3), input, X), " & "355 (BC_4, ETH1_RXCLK, observe_only, X), " & "354 (BC_1, ETH1_RXDV, input, X), " & "353 (BC_1, ETH1_CRS, input, X), " & "352 (BC_4, ETH1_TXCLK, observe_only, X), " & "351 (BC_2, *, control, 1), " & "350 (BC_1, ETH_MDIO, input, X), " & "349 (BC_1, ETH_MDIO, output3, X, 351, 1, Z), " & "348 (BC_1, ETH_MDC, output2, X), " & "347 (BC_1, ETH1_TXD(0), output2, X), " & "346 (BC_1, ETH1_TXD(1), output2, X), " & "345 (BC_1, ETH1_TXD(2), output2, X), " & "344 (BC_1, ETH1_TXD(3), output2, X), " & "343 (BC_1, ETH1_TXEN, output2, X), " & "342 (BC_2, *, controlr, 1), " & "341 (BC_1, GP2(0), input, X), " & "340 (BC_1, GP2(0), output3, X, 342, 1, PULL0)," & "339 (BC_2, *, controlr, 1), " & "338 (BC_1, GP2(1), input, X), " & "337 (BC_1, GP2(1), output3, X, 339, 1, PULL0)," & "336 (BC_2, *, controlr, 1), " & "335 (BC_1, GP2(2), input, X), " & "334 (BC_1, GP2(2), output3, X, 336, 1, PULL0)," & "333 (BC_2, *, controlr, 1), " & "332 (BC_1, GP2(3), input, X), " & "331 (BC_1, GP2(3), output3, X, 333, 1, PULL0)," & "330 (BC_2, *, controlr, 1), " & "329 (BC_1, GP2(4), input, X), " & "328 (BC_1, GP2(4), output3, X, 330, 1, Z), " & "327 (BC_2, *, controlr, 1), " & "326 (BC_1, GP2(5), input, X), " & "325 (BC_1, GP2(5), output3, X, 327, 1, Z), " & "324 (BC_2, *, controlr, 1), " & "323 (BC_1, GP2(6), input, X), " & "322 (BC_1, GP2(6), output3, X, 324, 1, Z), " & "321 (BC_2, *, controlr, 1), " & "320 (BC_1, GP2(7), input, X), " & "319 (BC_1, GP2(7), output3, X, 321, 1, Z), " & "318 (BC_2, *, controlr, 1), " & "317 (BC_1, GP2(8), input, X), " & "316 (BC_1, GP2(8), output3, X, 318, 1, Z), " & "315 (BC_2, *, controlr, 1), " & "314 (BC_1, GP2(9), input, X), " & "313 (BC_1, GP2(9), output3, X, 315, 1, Z), " & "312 (BC_2, *, controlr, 1), " & "311 (BC_1, GP2(10), input, X), " & "310 (BC_1, GP2(10), output3, X, 312, 1, PULL1)," & "309 (BC_2, *, controlr, 1), " & "308 (BC_1, GP2(11), input, X), " & "307 (BC_1, GP2(11), output3, X, 309, 1, PULL1)," & "306 (BC_2, *, controlr, 1), " & "305 (BC_1, GP2(12), input, X), " & "304 (BC_1, GP2(12), output3, X, 306, 1, PULL0)," & "303 (BC_2, *, controlr, 1), " & "302 (BC_1, GP2(13), input, X), " & "301 (BC_1, GP2(13), output3, X, 303, 1, PULL0)," & "300 (BC_2, *, controlr, 1), " & "299 (BC_1, GP2(14), input, X), " & "298 (BC_1, GP2(14), output3, X, 300, 1, PULL0)," & "297 (BC_2, *, controlr, 1), " & "296 (BC_1, GP2(15), input, X), " & "295 (BC_1, GP2(15), output3, X, 297, 1, PULL0)," & "294 (BC_2, *, controlr, 1), " & "293 (BC_1, PCI_STOP_N, input, X), " & "292 (BC_1, PCI_STOP_N, output3, X, 294, 1, Z), " & "291 (BC_2, *, controlr, 1), " & "290 (BC_1, PCI_PERR_N, input, X), " & "289 (BC_1, PCI_PERR_N, output3, X, 291, 1, Z), " & "288 (BC_2, *, controlr, 1), " & "287 (BC_1, PCI_DEVSEL_N, input, X), " & "286 (BC_1, PCI_DEVSEL_N, output3, X, 288, 1, Z), " & "285 (BC_2, *, controlr, 1), " & "284 (BC_1, PCI_INTA_N, output3, X, 285, 1, Z), " & "283 (BC_2, *, controlr, 1), " & "282 (BC_1, PCI_CLK, input, X), " & "281 (BC_1, PCI_CLK, output3, X, 283, 1, Z), " & "280 (BC_1, PCI_RST_N, input, X), " & "279 (BC_2, *, control, 1), " & "278 (BC_1, PCI_REQ_N, output3, X, 279, 1, Z), " & "277 (BC_1, PCI_GNT_N, input, X), " & "276 (BC_2, *, control, 1), " & "275 (BC_1, PCI_PME_N, output3, X, 276, 1, Z), " & "274 (BC_2, *, controlr, 1), " & "273 (BC_1, PCI_AD(0), input, X), " & "272 (BC_1, PCI_AD(0), output3, X, 274, 1, Z), " & "271 (BC_2, *, controlr, 1), " & "270 (BC_1, PCI_AD(1), input, X), " & "269 (BC_1, PCI_AD(1), output3, X, 271, 1, Z), " & "268 (BC_2, *, controlr, 1), " & "267 (BC_1, PCI_AD(2), input, X), " & "266 (BC_1, PCI_AD(2), output3, X, 268, 1, Z), " & "265 (BC_2, *, controlr, 1), " & "264 (BC_1, PCI_AD(3), input, X), " & "263 (BC_1, PCI_AD(3), output3, X, 265, 1, Z), " & "262 (BC_2, *, controlr, 1), " & "261 (BC_1, PCI_AD(4), input, X), " & "260 (BC_1, PCI_AD(4), output3, X, 262, 1, Z), " & "259 (BC_2, *, controlr, 1), " & "258 (BC_1, PCI_AD(5), input, X), " & "257 (BC_1, PCI_AD(5), output3, X, 259, 1, Z), " & "256 (BC_2, *, controlr, 1), " & "255 (BC_1, PCI_AD(6), input, X), " & "254 (BC_1, PCI_AD(6), output3, X, 256, 1, Z), " & "253 (BC_2, *, controlr, 1), " & "252 (BC_1, PCI_AD(7), input, X), " & "251 (BC_1, PCI_AD(7), output3, X, 253, 1, Z), " & "250 (BC_2, *, controlr, 1), " & "249 (BC_1, PCI_AD(8), input, X), " & "248 (BC_1, PCI_AD(8), output3, X, 250, 1, Z), " & "247 (BC_2, *, controlr, 1), " & "246 (BC_1, PCI_AD(9), input, X), " & "245 (BC_1, PCI_AD(9), output3, X, 247, 1, Z), " & "244 (BC_2, *, controlr, 1), " & "243 (BC_1, PCI_AD(10), input, X), " & "242 (BC_1, PCI_AD(10), output3, X, 244, 1, Z), " & "241 (BC_2, *, controlr, 1), " & "240 (BC_1, PCI_AD(11), input, X), " & "239 (BC_1, PCI_AD(11), output3, X, 241, 1, Z), " & "238 (BC_2, *, controlr, 1), " & "237 (BC_1, PCI_AD(12), input, X), " & "236 (BC_1, PCI_AD(12), output3, X, 238, 1, Z), " & "235 (BC_2, *, controlr, 1), " & "234 (BC_1, PCI_AD(13), input, X), " & "233 (BC_1, PCI_AD(13), output3, X, 235, 1, Z), " & "232 (BC_2, *, controlr, 1), " & "231 (BC_1, PCI_AD(14), input, X), " & "230 (BC_1, PCI_AD(14), output3, X, 232, 1, Z), " & "229 (BC_2, *, controlr, 1), " & "228 (BC_1, PCI_AD(15), input, X), " & "227 (BC_1, PCI_AD(15), output3, X, 229, 1, Z), " & "226 (BC_2, *, controlr, 1), " & "225 (BC_1, PCI_AD(16), input, X), " & "224 (BC_1, PCI_AD(16), output3, X, 226, 1, Z), " & "223 (BC_2, *, controlr, 1), " & "222 (BC_1, PCI_AD(17), input, X), " & "221 (BC_1, PCI_AD(17), output3, X, 223, 1, Z), " & "220 (BC_2, *, controlr, 1), " & "219 (BC_1, PCI_AD(18), input, X), " & "218 (BC_1, PCI_AD(18), output3, X, 220, 1, Z), " & "217 (BC_2, *, controlr, 1), " & "216 (BC_1, PCI_AD(19), input, X), " & "215 (BC_1, PCI_AD(19), output3, X, 217, 1, Z), " & "214 (BC_2, *, controlr, 1), " & "213 (BC_1, PCI_AD(20), input, X), " & "212 (BC_1, PCI_AD(20), output3, X, 214, 1, Z), " & "211 (BC_2, *, controlr, 1), " & "210 (BC_1, PCI_AD(21), input, X), " & "209 (BC_1, PCI_AD(21), output3, X, 211, 1, Z), " & "208 (BC_2, *, controlr, 1), " & "207 (BC_1, PCI_AD(22), input, X), " & "206 (BC_1, PCI_AD(22), output3, X, 208, 1, Z), " & "205 (BC_2, *, controlr, 1), " & "204 (BC_1, PCI_AD(23), input, X), " & "203 (BC_1, PCI_AD(23), output3, X, 205, 1, Z), " & "202 (BC_2, *, controlr, 1), " & "201 (BC_1, PCI_AD(24), input, X), " & "200 (BC_1, PCI_AD(24), output3, X, 202, 1, Z), " & "199 (BC_2, *, controlr, 1), " & "198 (BC_1, PCI_AD(25), input, X), " & "197 (BC_1, PCI_AD(25), output3, X, 199, 1, Z), " & "196 (BC_2, *, controlr, 1), " & "195 (BC_1, PCI_AD(26), input, X), " & "194 (BC_1, PCI_AD(26), output3, X, 196, 1, Z), " & "193 (BC_2, *, controlr, 1), " & "192 (BC_1, PCI_AD(27), input, X), " & "191 (BC_1, PCI_AD(27), output3, X, 193, 1, Z), " & "190 (BC_2, *, controlr, 1), " & "189 (BC_1, PCI_AD(28), input, X), " & "188 (BC_1, PCI_AD(28), output3, X, 190, 1, Z), " & "187 (BC_2, *, controlr, 1), " & "186 (BC_1, PCI_AD(29), input, X), " & "185 (BC_1, PCI_AD(29), output3, X, 187, 1, Z), " & "184 (BC_2, *, controlr, 1), " & "183 (BC_1, PCI_AD(30), input, X), " & "182 (BC_1, PCI_AD(30), output3, X, 184, 1, Z), " & "181 (BC_2, *, controlr, 1), " & "180 (BC_1, PCI_AD(31), input, X), " & "179 (BC_1, PCI_AD(31), output3, X, 181, 1, Z), " & "178 (BC_2, *, controlr, 1), " & "177 (BC_1, PCI_CBE_N(0), input, X), " & "176 (BC_1, PCI_CBE_N(0), output3, X, 178, 1, Z), " & "175 (BC_2, *, controlr, 1), " & "174 (BC_1, PCI_CBE_N(1), input, X), " & "173 (BC_1, PCI_CBE_N(1), output3, X, 175, 1, Z), " & "172 (BC_2, *, controlr, 1), " & "171 (BC_1, PCI_CBE_N(2), input, X), " & "170 (BC_1, PCI_CBE_N(2), output3, X, 172, 1, Z), " & "169 (BC_2, *, controlr, 1), " & "168 (BC_1, PCI_CBE_N(3), input, X), " & "167 (BC_1, PCI_CBE_N(3), output3, X, 169, 1, Z), " & "166 (BC_2, *, controlr, 1), " & "165 (BC_1, PCI_PAR, input, X), " & "164 (BC_1, PCI_PAR, output3, X, 166, 1, Z), " & "163 (BC_2, *, controlr, 1), " & "162 (BC_1, PCI_IRDY_N, input, X), " & "161 (BC_1, PCI_IRDY_N, output3, X, 163, 1, Z), " & "160 (BC_2, *, controlr, 1), " & "159 (BC_1, PCI_FRAME_N, input, X), " & "158 (BC_1, PCI_FRAME_N, output3, X, 160, 1, Z), " & "157 (BC_1, PCI_IDSEL, input, X), " & "156 (BC_2, *, control, 1), " & "155 (BC_1, PCI_SERR_N, output3, X, 156, 1, Z), " & "154 (BC_2, *, controlr, 1), " & "153 (BC_1, PCI_TRDY_N, input, X), " & "152 (BC_1, PCI_TRDY_N, output3, X, 154, 1, Z), " & "151 (BC_1, MICS(0), output2, X), " & "150 (BC_1, MICS(1), output2, X), " & "149 (BC_1, MICS(2), output2, X), " & "148 (BC_1, MICS(3), output2, X), " & "147 (BC_1, MIA(0), output2, X), " & "146 (BC_1, MIA(1), output2, X), " & "145 (BC_1, MIA(2), output2, X), " & "144 (BC_1, MIA(3), output2, X), " & "143 (BC_1, MIA(4), output2, X), " & "142 (BC_1, MIA(5), output2, X), " & "141 (BC_1, MIA(6), output2, X), " & "140 (BC_1, MIA(7), output2, X), " & "139 (BC_1, MIA(8), output2, X), " & "138 (BC_1, MIA(9), output2, X), " & "137 (BC_1, MIA(10), output2, X), " & "136 (BC_1, MIA(11), output2, X), " & "135 (BC_1, MIA(12), output2, X), " & "134 (BC_1, MIA(13), output2, X), " & "133 (BC_1, MIA(14), output2, X), " & "132 (BC_1, MIA(15), output2, X), " & "131 (BC_1, MIRDY, input, X), " & "130 (BC_1, MICLKEN, output2, X), " & "129 (BC_1, MIOE, output2, X), " & "128 (BC_1, MISA, output2, X), " & "127 (BC_1, MIWE, output2, X), " & "126 (BC_1, MIAA, output2, X), " & "125 (BC_2, *, control, 1), " & "124 (BC_1, MID(0), input, X), " & "123 (BC_1, MID(0), output3, X, 125, 1, Z), " & "122 (BC_2, *, control, 1), " & "121 (BC_1, MID(1), input, X), " & "120 (BC_1, MID(1), output3, X, 122, 1, Z), " & "119 (BC_2, *, control, 1), " & "118 (BC_1, MID(2), input, X), " & "117 (BC_1, MID(2), output3, X, 119, 1, Z), " & "116 (BC_2, *, control, 1), " & "115 (BC_1, MID(3), input, X), " & "114 (BC_1, MID(3), output3, X, 116, 1, Z), " & "113 (BC_2, *, control, 1), " & "112 (BC_1, MID(4), input, X), " & "111 (BC_1, MID(4), output3, X, 113, 1, Z), " & "110 (BC_2, *, control, 1), " & "109 (BC_1, MID(5), input, X), " & "108 (BC_1, MID(5), output3, X, 110, 1, Z), " & "107 (BC_2, *, control, 1), " & "106 (BC_1, MID(6), input, X), " & "105 (BC_1, MID(6), output3, X, 107, 1, Z), " & "104 (BC_2, *, control, 1), " & "103 (BC_1, MID(7), input, X), " & "102 (BC_1, MID(7), output3, X, 104, 1, Z), " & "101 (BC_2, *, control, 1), " & "100 (BC_1, MID(8), input, X), " & "99 (BC_1, MID(8), output3, X, 101, 1, Z), " & "98 (BC_2, *, control, 1), " & "97 (BC_1, MID(9), input, X), " & "96 (BC_1, MID(9), output3, X, 98, 1, Z), " & "95 (BC_2, *, control, 1), " & "94 (BC_1, MID(10), input, X), " & "93 (BC_1, MID(10), output3, X, 95, 1, Z), " & "92 (BC_2, *, control, 1), " & "91 (BC_1, MID(11), input, X), " & "90 (BC_1, MID(11), output3, X, 92, 1, Z), " & "89 (BC_2, *, control, 1), " & "88 (BC_1, MID(12), input, X), " & "87 (BC_1, MID(12), output3, X, 89, 1, Z), " & "86 (BC_2, *, control, 1), " & "85 (BC_1, MID(13), input, X), " & "84 (BC_1, MID(13), output3, X, 86, 1, Z), " & "83 (BC_2, *, control, 1), " & "82 (BC_1, MID(14), input, X), " & "81 (BC_1, MID(14), output3, X, 83, 1, Z), " & "80 (BC_2, *, control, 1), " & "79 (BC_1, MID(15), input, X), " & "78 (BC_1, MID(15), output3, X, 80, 1, Z), " & "77 (BC_1, MIBLS(0), output2, X), " & "76 (BC_1, MIBLS(1), output2, X), " & "75 (BC_1, MIBLS(2), output2, X), " & "74 (BC_1, MIBLS(3), output2, X), " & "73 (BC_4, HFCLK, observe_only, X), " & "72 (BC_1, LNA_HIGHGAIN, output2, X), " & "71 (BC_2, *, control, 1), " & "70 (BC_1, GP1(0), input, X), " & "69 (BC_1, GP1(0), output3, X, 71, 1, PULL0)," & "68 (BC_2, *, controlr, 1), " & "67 (BC_1, GP1(1), input, X), " & "66 (BC_1, GP1(1), output3, X, 68, 1, PULL0)," & "65 (BC_2, *, controlr, 1), " & "64 (BC_1, GP1(2), input, X), " & "63 (BC_1, GP1(2), output3, X, 65, 1, PULL1)," & "62 (BC_2, *, controlr, 1), " & "61 (BC_1, GP1(3), input, X), " & "60 (BC_1, GP1(3), output3, X, 62, 1, PULL0)," & "59 (BC_2, *, controlr, 1), " & "58 (BC_1, GP1(4), input, X), " & "57 (BC_1, GP1(4), output3, X, 59, 1, PULL0)," & "56 (BC_2, *, controlr, 1), " & "55 (BC_1, GP1(5), input, X), " & "54 (BC_1, GP1(5), output3, X, 56, 1, PULL0)," & "53 (BC_2, *, controlr, 1), " & "52 (BC_1, GP1(6), input, X), " & "51 (BC_1, GP1(6), output3, X, 53, 1, PULL0)," & "50 (BC_2, *, controlr, 1), " & "49 (BC_1, GP1(7), input, X), " & "48 (BC_1, GP1(7), output3, X, 50, 1, PULL0)," & "47 (BC_2, *, controlr, 1), " & "46 (BC_1, GP1(8), input, X), " & "45 (BC_1, GP1(8), output3, X, 47, 1, PULL0)," & "44 (BC_2, *, controlr, 1), " & "43 (BC_1, GP1(9), input, X), " & "42 (BC_1, GP1(9), output3, X, 44, 1, PULL0)," & "41 (BC_2, *, controlr, 1), " & "40 (BC_1, GP1(10), input, X), " & "39 (BC_1, GP1(10), output3, X, 41, 1, PULL0)," & "38 (BC_2, *, controlr, 1), " & "37 (BC_1, GP1(11), input, X), " & "36 (BC_1, GP1(11), output3, X, 38, 1, PULL0)," & "35 (BC_2, *, controlr, 1), " & "34 (BC_1, GP1(12), input, X), " & "33 (BC_1, GP1(12), output3, X, 35, 1, PULL1)," & "32 (BC_2, *, controlr, 1), " & "31 (BC_1, GP1(13), input, X), " & "30 (BC_1, GP1(13), output3, X, 32, 1, PULL0)," & "29 (BC_2, *, controlr, 1), " & "28 (BC_1, GP1(14), input, X), " & "27 (BC_1, GP1(14), output3, X, 29, 1, PULL1)," & "26 (BC_2, *, controlr, 1), " & "25 (BC_1, GP1(15), input, X), " & "24 (BC_1, GP1(15), output3, X, 26, 1, PULL1)," & "23 (BC_2, *, controlr, 1), " & "22 (BC_1, GP3(0), input, X), " & "21 (BC_1, GP3(0), output3, X, 23, 1, PULL1)," & "20 (BC_2, *, controlr, 1), " & "19 (BC_1, GP3(1), input, X), " & "18 (BC_1, GP3(1), output3, X, 20, 1, PULL1)," & "17 (BC_2, *, controlr, 1), " & "16 (BC_1, GP3(2), input, X), " & "15 (BC_1, GP3(2), output3, X, 17, 1, PULL1)," & "14 (BC_2, *, controlr, 1), " & "13 (BC_1, GP3(3), input, X), " & "12 (BC_1, GP3(3), output3, X, 14, 1, PULL1)," & "11 (BC_2, *, controlr, 1), " & "10 (BC_1, GP3(4), input, X), " & "9 (BC_1, GP3(4), output3, X, 11, 1, PULL1)," & "8 (BC_2, *, controlr, 1), " & "7 (BC_1, GP3(5), input, X), " & "6 (BC_1, GP3(5), output3, X, 8, 1, PULL0)," & "5 (BC_2, *, controlr, 1), " & "4 (BC_1, GP3(6), input, X), " & "3 (BC_1, GP3(6), output3, X, 5, 1, PULL1)," & "2 (BC_2, *, controlr, 1), " & "1 (BC_1, GP3(7), input, X), " & "0 (BC_1, GP3(7), output3, X, 2, 1, PULL0)"; end isl3893;